Soft Error Hardened Latch
Mater. (2000 - 2015) Semicond. The proposed circuit has low power consumption with negative setup time and low timing overhead. The soft error immunity of the latch is estimated by device simulation more accurately. of Solid-State Circuits 44(1), 32–48 (2009)CrossRef15.Dabiri, F., Nahapetian, A., Massey, T., Potkonjak, M., Sarrafzadeh, M.: General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing. Source
In other words, sequential logic has memory while combinational logic does not. Mater. (2006 - present) Biomed. The proposed latches are fully SEU immune, i.e. IEEE Trans. http://ieeexplore.ieee.org/iel5/5116585/5116586/05116607.pdf?arnumber=5116607
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- Keywords soft-error static latch hardened latch reliability Page %P Close Plain text Look Inside Chapter Metrics Provided by Bookmetrix Reference tools Export citation EndNote (.ENW) JabRef (.BIB) Mendeley (.BIB) Papers (.RIS)
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The system returned: (22) Invalid argument The remote host or network may be down. Citing articles (0) This article has not been cited. Topogr.: Metrol. Sci.
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of Solid-State Circuits 44(1), 18–31 (2009)CrossRef20.Degalahal, V., Ramanarayanan, R., Vijaykrishnan, N., Xie, Y., Irwin, M.J.: Effect of Power Optimizations on Soft Error Rate.
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